A technique to design a broadband two-stage frequency tripler is proposed. The 1st and the 2nd harmonics obtained from the first stage are mixed in the second stage, getting the 3rd harmonic. Between the two stages, there is a two-pole filter which lets the amplitude of the 1st harmonic increase and the amplitude of the 2nd harmonic decrease when the frequency increases. Consequently, a large 1st harmonic is always mixed with a small 2nd harmonic, and vice versa, which equalizes the amplitude of the mixing product, i.e., the 3rd harmonic, over a large bandwidth. Together with a frequency doubler and a buffer amplifier, this frequency tripler is used in a frequency sixtupler. A proof-of-concept circuit is designed and implemented in 250 nm indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology. For an input power of 6.3 dBm, the sixtupler has an output power between 0 dBm to 4.6 dBm in the output frequency range from 135 GHz to 183 GHz. It exhibits up to 13 dBc rejection ratio of the undesired 4th, 5th, and 7th harmonics. The sixtupler consumes a dc power of 100 mW, and achieves a peak power efficiency of 2.5%.